李胜高博士 - 台积电处长

关于

李胜高博士是高速SerDes、芯粒、3D-IC及光互连领域公认的专家，拥有逾20年在半导体行业推动创新解决方案的丰富经验。他在模拟与混合信号设计理论与实践、射频设计、锁相环及高速电子学等领域积累了深厚的专业知识。

他最近担任台积电设计与技术平台高速互连处长，专注于高能效互连技术研发，涵盖芯粒与3D-IC互连（UCIe与HBM物理层）、面向无线与有线通信的高速模数转换器，以及200-400G共封装光学器件。

加入台积电之前，李博士曾在英特尔担任首席工程师、部门负责人及IP/SoC战略总监，主导PCIe Gen3.0/4.0/5.0、UPI及CXL PHY的实现与高良率量产（跨越32nm至7nm共五代至强处理器产品），并推动公司层面冗余IP的战略整合。

李博士现任IEEE CICC技术程序委员会主席，并担任UCIe封装规格与合规工作组联合主席。他近期已暂别大企业职业生涯，正积极筹备新的创业计划，致力于攻克下一代计算集群中高能效、高带宽互连的前沿挑战。

                    教育背景
                    访问科学家
麻省理工学院 (MIT)
商业高管课程
企业创新
斯坦福大学商学院
电气工程博士
俄亥俄州立大学（哥伦布）
硕士
清华大学（北京）
学士
西北工业大学（西安）

                

代表性论文

2026

A Decision Feed-Forward Equalizer with Error Detection and Correction for 200-400Gbps Wireline Applications

IEEE Open Journal of the Solid-State Circuits Society

Shenggao Li, Maher Amer

doi.org/10.1109/OJSSCS.2026.3708104
A 32Gb/s 12.35Tb/s/mm² 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging

IEEE International Solid-State Circuits Conference (ISSCC 2026)

Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, et al.

2025

Design and Implementation of RF Circuit Under Inductor (CUI) in CMOS Technologies

IEEE Transactions on Microwave Theory and Techniques (Early Access)

Hsieh-Hung Hsieh, Shenggao Li, et al.
Design Technology Co-optimization for RF/mmWave Circuits with Circuit under Inductor (CUI) in FinFET CMOS Technologies

IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2025)

Hsieh-Hung Hsieh, Shenggao Li, et al.
A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

IEEE International Solid-State Circuits Conference (ISSCC 2025)

Mu-Shan Lin, Shenggao Li, et al.
UCIe-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies

IEEE Custom Integrated Circuits Conference (CICC 2025)

Yu-Jie Huang, Mu-Shan Lin, Shenggao Li, et al.
Fast and Accurate Jitter Amplification Modeling With Variable Pulse Width Response

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 15(4)

Shenggao Li, Maher Amer
TSMC in the Silicon Photonics Era - an Electrical Perspective

Optical Fiber Communication Conference (OFC 2025)

Mikael Sahrling, Shenggao Li, Frank Lee, Stefan Rusu

2024

High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions

IEEE Open Journal of the Solid-State Circuits Society

Shenggao Li, Mu-Shan Lin, Wei-Chih Chen, Chien-Chun Tsai
Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process

IEEE Symposium on VLSI Technology and Circuits 2024

Chu-En Hsia, Shenggao Li, et al.
A 0.296pJ/bit 17.9Tb/s/mm² Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package

IEEE Symposium on VLSI Technology and Circuits 2024

Mu-Shan Lin, Shenggao Li, et al.

2022

Interconnect in the Era of 3DIC

IEEE Custom Integrated Circuits Conference (CICC 2022)

Shenggao Li et al.

2018

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS

IEEE Asian Solid-State Circuits Conference (A-SSCC 2018)

Shenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, et al.

2014-2015

A 22nm 15-Core Enterprise Xeon Processor Family

IEEE International Solid-State Circuits Conference (ISSCC 2014) & IEEE Journal of Solid-State Circuits, Vol. 50(1), 2015

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, et al.

2011

Clock Generation for a 32nm Server Processor with Scalable Cores

IEEE International Solid-State Circuits Conference (ISSCC 2011)

Shenggao Li, Ashwin Krishnakumar, Edward Helder, Roan Nicholson, Vivian Jia

2003

A 10-GHz CMOS Quadrature LC-VCO for Multirate Optical Applications

IEEE Journal of Solid-State Circuits, Vol. 38(10), pp. 1626-1634

Shenggao Li, Issy Kipnis, Mohammed Ismail

企业论文发表

台积电 DTP 会议

A 23fJ/bit PAM4 224Gbps Non-retimed Optical Receiver for COUPE Application

Gaurav Yadav, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2025
A 12bit 400MS/s TDC-Assisted SAR ADC

Manoj Bharat Vasekar, Mei-Chen Chuang, Shenggao Li

DTP Conference 2025
Topology Transferable Graph Neural Networks with Reinforcement Learning for Circuit Scalable DTCO

Chih-Chiang Lin, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2025
An A16 SPR 0.246pJ/bit 64Gb/s/pin UCIe-Compliant Receiver with PWM-based DFE and Efficient Per-lane DCC/QEC Calibration

Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2025（最佳论文奖）
A 64Gbps 21Tb/s/mm 0.548pJ/bit 3nm Chiplet System on Both CoWoS-L and CoWoS-R Advanced Packaging and AI-Driven Prediction for Next Generation Multi-Stacked 2.5D Packaging

Shu-Chun Yang, Wei-Chih Chen, Chien-Chun Tsai, Shenggao Li

DTP Conference 2025（最佳报告奖）
A 32Gb/s 10.5Tb/s/mm 0.34pJ/bit Chiplet IO Using CoWoS-L Active-LSI with Edge Trigger Transceiver in 3nm

Chin-Hua Wen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2024（最佳论文奖）
A 2-16GHz 0.66° 85-fs p-p Jitter Precise Quadrature Clock Generator with Chopping Cancellation and Dynamic Gating Mode

Wei-Shuo Lin, Wei-Chin Chen, Chien-Chun Tsai, Shenggao Li

DTP Conference 2024
Ring-Amplifier-Based CDAC Reference Buffer with Auxiliary Stages for Fast Settling Improvements

Shang-Hsien Yang, Mei-Chen Chuang, Shenggao Li

DTP Conference 2024
A 64Gb/s 0.232pJ/b 3nm NRZ Transmitter Using CoWoS-L with Capacitive Equalization and Edge-Complementary Zero-Crossing Sampling

Sheng-Tsung Lai, Shu-Chun Yang, Han-Tzung Ke, Wei-Chih Chen, Chien-Chun Tsai, Shenggao Li

DTP Conference 2024
Wafer-Scale Optical Interconnects: All-to-all Link for Bandwidth of 10TBps per ASIC and 3360TBps on a Wafer

Gaurav Vijay Yadav, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2024
A 3nm 0.27pJ/bit 32Gb/s/pin UCIe-Compliant Receiver with Matched-delay Architecture and Deskew/Runtime Calibration

Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2023（最佳论文奖）
A 0.4pJ/b 32Gb/s Die-to-Die Link Using NRZ Transmitter with Arbitrary Clock Phases and Low Latency for 10.5Tb/s/mm UCIe Applications in 3nm FinFET

Chin-Hua Wen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2023
Statistical Bit Error Rate Analysis for Die to Die Interconnect – A Tutorial

Shenggao Li

DTP Conference 2023
Jitter Modeling and Analysis for High-Speed Communication Systems (A Tutorial)

Shenggao Li, Maher Amer

DTP Conference 2022
A 2.4mW 6b 400μm² 1.75GS/s SAR ADC with Delay-Reduction Schemes and Consolidated P/N Guard-Ring Pickup Tap in 5nm FinFET CMOS

Mei-Chen Chuang, Shenggao Li, et al.

DTP Conference 2022（最佳报告奖）
A 7nm 8Gb/s/pin LIPINCON Chiplet Interface with 2Tbit/s/mm Beachfront Bandwidth Density and 0.36pJ/bit Energy Efficiency for GPGPU Application

Yu-Jie Huang, Shenggao Li, et al.

DTP Conference 2022（最佳论文奖）
A 5nm/6nm 16Gb/s/pin PAM4 Cross-Chiplets Link Achieving 1280GB/s Bandwidth, 0.296pJ/bit Energy Efficiency, and 17.9Tb/s/mm² Area Efficiency for 3DIC Applications

Mu-Shan Lin, Shenggao Li, et al.

DTP Conference 2021（最佳论文奖）
Multi-Path 16GHz 8-phase Ring Oscillator with Better Voltage Sensitivity by 4nm Technology

Shenggao Li, et al.

DTP Conference 2021

英特尔 DTTC 会议

An All-Digital CMOS Ring-oscillator based Clock Data Recovery System for Multi-rate Serial Links

Shenggao Li, et al.

Intel DTTC 2017
Nonlinearity in a Non-integrating DFE Summer

Xiaoqing Wang, Shenggao Li

Intel DTTC 2017
The Pursuit of a Crosstalk Tolerant Forwarded-Clock System – A Case Study

Kai Xiao, Shenggao Li, et al.

Intel DTTC 2013
IVT PCIE/QPI DFE Summer – Post-Silicon Learnings and Design Optimization

Salman Latif, Shenggao Li, et al.

Intel DTTC 2013
LC-PLL with Digital Frequency Calibration and Improved HVM Screening

Roan Nicholson, Shenggao Li, et al.

Intel DTTC 2013
High-speed Low-power Clock Dividers for Phase-locked Loops (Tutorial)

Shenggao Li

Intel DTTC 2011

专利

已授权专利（2000–2024）

US10,848,353 - Multi-Tap Decision Feedback Equalizer (DFE) Architecture with Split-Path Summer Circuits

授权：2019年6月
US10,708,093 - Supply Voltage Adaptation Via Decision Feedback Equalizer

授权：2018年8月
US10,523,411 - Programmable Clock Data Recovery (CDR) System Including Multiple Phase Error Control Paths

授权：2018年3月
US10,181,969 - High Performance Receiver with Single Calibration

授权：2019年1月
US10,128,855 - Apparatus and Method for Clock Synchronization for Inter-Die Synchronized Data Transfer

授权：2018年11月
US10,075,308 - Supply Voltage Adaptation Via Decision Feedback Equalizer

授权：2018年9月
US10,063,253 - Summer Circuit Including Linearized Load

授权：2018年8月
US9,973,176 - Circuits for Digital and Analog Controlled Oscillators

授权：2018年5月
US9,735,813 - Method and Apparatus for Signal Edge Boosting

授权：2017年8月
US9,641,184 - Compensation for Digitally Controlled Oscillator Apparatus and Method

授权：2017年5月
US9,531,393 - Phase Frequency Detector

授权：2016年12月
US9,455,727 - Open-Loop Voltage Regulation and Drift Compensation for Digitally Controlled Oscillator (DCO)

授权：2016年9月
US9,413,364 - Apparatus and Method for Clock Synchronization for Inter-Die Synchronized Data Transfer

授权：2016年8月
US9,379,743 - Method and Apparatus for Signal Edge Boosting

授权：2016年6月
US9,215,104 - Floating Taps for Decision Feedback Equalizer

授权：2015年12月
US9,071,253 - Compensation for Digitally Controlled Oscillator App. and Method

授权：2015年6月
US8,981,822 - High Speed Dual Modulus Divider

授权：2015年3月
US8,957,705 - Phase Frequency Detector

授权：2015年2月
US8,843,093 - Low Power Squelch Detector Circuit

授权：2014年9月
US8,749,289 - Multi-Phase Clock Generation Apparatus and Method

授权：2014年6月
US8,520,428 - Combined Data Level-Shifter and De-Skewer

授权：2013年8月
US7,421,052 - Oscillator Frequency Selection

授权：2008年9月
US7,366,427 - Line Driver with Variable Bandwidth Control

授权：2008年4月
US6,954,110 - Replica Cell for Ring Oscillator

授权：2005年10月
US6,870,432 - Unilateral Coupling for a Quadrature Voltage Controlled Oscillator

授权：2005年3月
US6,853,254 - Anti-Deadlock Circuit and Method for Phase-Locked Loops

授权：2005年2月

近期专利申请（2020–2024）

Differential Magnetic Core Inductors in Silicon Wafer or THV/TGV

与普林斯顿大学及宾夕法尼亚大学联合临时发明专利

申请：2025年7月
18/919,584 - 3D Die to Die Interconnect Clock Scheme

申请：2024年10月
18/912,708 - Universal Bump Map Assignment for 3D Lego Stacking

申请：2024年10月
18/815,990 - Synchronized Clock Distribution Between Two Vertically Stacked Dies

申请：2024年8月
18/779,308 - Settling-Time Reduction Technique for Continuous Time Comparators

申请：2024年7月
18/772,677 - Clock Scheme for Die to Die Interconnect with Maximal I/F Timing Robustness

申请：2024年7月
18/768,508 - 3D Die Stacking and Bump Organization Method

申请：2024年7月
18/749,857 - Fine Granularity Control of Digitally Controlled Multi-Phase Delay Line and/or Ring Oscillator

申请：2024年6月
18/647,151 - In-situ Defect Detection and Monitoring with Ability to Boost ADC Accuracy

申请：2024年4月
18/623,579 - Chiplet Interconnect Method for Better EM/IR Performance

申请：2024年4月
18/436,643 - Using Honeycomb Structure for Die to Die Interconnect Structures

申请：2024年2月（已授权）
18/517,078 - Defect Characterization and Monitoring Mechanism for Better Yield Analysis

申请：2023年11月
18/348,422 - A CDAC Control Method with Monotonicity Behavior

申请：2023年7月
18/300,862 - Using Honeycomb Structure for Die to Die Interconnect Structures

申请：2023年4月（已授权）
18/239,839 - A Delay Line Implementation Method to Decouple High-Speed Path and Low Speed Control

申请：2023年8月
18/194,709 - 2.5D/3D Die to Die Integration Method to Enable Symmetry and High Bandwidth Density

申请：2023年4月
18/128,601 - Hybrid or Clusters of Power Bumps for Advanced Packaging

申请：2023年3月
17/825,360 - Eliminate Impact of TSV IR Drop for On-Die Voltage Regulator in 3DIC Integration

申请：2022年5月
17/688,966 - High-Voltage Design Methodology

申请：2022年3月

特邀演讲与主旨报告

Scaling AI Beyond Moore's Law: Serdes, 3D-IC Interconnects, Silicon Photonics, and DTCO for the Next Generation of Computing

Texas Semiconductor Summit，德克萨斯农工大学

主旨演讲 | 2026年3月26日
Energy-Efficient Computing and Communication

半导体研讨系列讲座，韦恩州立大学

特邀演讲 | 2026年3月25日
Enabling Energy-Efficient High-speed Interconnects and Photonic Networks

研讨会："面向AI基础设施的光子交换：构建下一代AI互连架构" | OFC 2026，洛杉矶会议中心

特邀嘉宾 | 2026年3月18日
Energy Efficient Computing and Communication: Perspectives on Chiplet Interconnects and Photonic Networks

MIT MTL CICS 研讨会

特邀演讲 | 2026年2月18日
Towards 400G+ bps Energy Efficient Optical Networks

MIT Rodgers RLE Forum 演讲与问答

特邀演讲 | 2026年2月 | 链接（需MIT Zoom账号）
Towards 400G+ bps Per Lane Optical Networks for AI/ML Applications

SRC Jump 2.0 CUbiC（无处不在连接中心），哥伦比亚大学

特邀演讲 | 2025年7月
Automotive Chiplets

工程学院产学合作论坛，韦恩州立大学

主旨演讲 | 2024年10月
Advanced Packaging and 3D-IC Interconnects

ISSCC 2023 Forum 1：Exascale 级收发器

特邀演讲 | 2023年2月
Interconnect in the Era of 3DIC

IEEE Custom Integrated Circuits Conference (CICC 2022)

行业演讲 | 2022年4月

关于

教育背景

工作经历

设计与技术平台高速互连处长

IP/SoC战略总监 | 首席工程师兼部门负责人

代表性论文

A Decision Feed-Forward Equalizer with Error Detection and Correction for 200-400Gbps Wireline Applications

A 32Gb/s 12.35Tb/s/mm² 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging

Design and Implementation of RF Circuit Under Inductor (CUI) in CMOS Technologies

Design Technology Co-optimization for RF/mmWave Circuits with Circuit under Inductor (CUI) in FinFET CMOS Technologies

A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

UCIe-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies

Fast and Accurate Jitter Amplification Modeling With Variable Pulse Width Response

TSMC in the Silicon Photonics Era - an Electrical Perspective

High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions

Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process

A 0.296pJ/bit 17.9Tb/s/mm² Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package

Interconnect in the Era of 3DIC

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS

A 22nm 15-Core Enterprise Xeon Processor Family

Clock Generation for a 32nm Server Processor with Scalable Cores

A 10-GHz CMOS Quadrature LC-VCO for Multirate Optical Applications

企业论文发表

台积电 DTP 会议

A 23fJ/bit PAM4 224Gbps Non-retimed Optical Receiver for COUPE Application

A 12bit 400MS/s TDC-Assisted SAR ADC

Topology Transferable Graph Neural Networks with Reinforcement Learning for Circuit Scalable DTCO

An A16 SPR 0.246pJ/bit 64Gb/s/pin UCIe-Compliant Receiver with PWM-based DFE and Efficient Per-lane DCC/QEC Calibration

A 64Gbps 21Tb/s/mm 0.548pJ/bit 3nm Chiplet System on Both CoWoS-L and CoWoS-R Advanced Packaging and AI-Driven Prediction for Next Generation Multi-Stacked 2.5D Packaging

A 32Gb/s 10.5Tb/s/mm 0.34pJ/bit Chiplet IO Using CoWoS-L Active-LSI with Edge Trigger Transceiver in 3nm

A 2-16GHz 0.66° 85-fs p-p Jitter Precise Quadrature Clock Generator with Chopping Cancellation and Dynamic Gating Mode

Ring-Amplifier-Based CDAC Reference Buffer with Auxiliary Stages for Fast Settling Improvements

A 64Gb/s 0.232pJ/b 3nm NRZ Transmitter Using CoWoS-L with Capacitive Equalization and Edge-Complementary Zero-Crossing Sampling

Wafer-Scale Optical Interconnects: All-to-all Link for Bandwidth of 10TBps per ASIC and 3360TBps on a Wafer

A 3nm 0.27pJ/bit 32Gb/s/pin UCIe-Compliant Receiver with Matched-delay Architecture and Deskew/Runtime Calibration

A 0.4pJ/b 32Gb/s Die-to-Die Link Using NRZ Transmitter with Arbitrary Clock Phases and Low Latency for 10.5Tb/s/mm UCIe Applications in 3nm FinFET

Statistical Bit Error Rate Analysis for Die to Die Interconnect – A Tutorial

Jitter Modeling and Analysis for High-Speed Communication Systems (A Tutorial)

A 2.4mW 6b 400μm² 1.75GS/s SAR ADC with Delay-Reduction Schemes and Consolidated P/N Guard-Ring Pickup Tap in 5nm FinFET CMOS

A 7nm 8Gb/s/pin LIPINCON Chiplet Interface with 2Tbit/s/mm Beachfront Bandwidth Density and 0.36pJ/bit Energy Efficiency for GPGPU Application

A 5nm/6nm 16Gb/s/pin PAM4 Cross-Chiplets Link Achieving 1280GB/s Bandwidth, 0.296pJ/bit Energy Efficiency, and 17.9Tb/s/mm² Area Efficiency for 3DIC Applications

Multi-Path 16GHz 8-phase Ring Oscillator with Better Voltage Sensitivity by 4nm Technology

英特尔 DTTC 会议

An All-Digital CMOS Ring-oscillator based Clock Data Recovery System for Multi-rate Serial Links

Nonlinearity in a Non-integrating DFE Summer

The Pursuit of a Crosstalk Tolerant Forwarded-Clock System – A Case Study

IVT PCIE/QPI DFE Summer – Post-Silicon Learnings and Design Optimization

LC-PLL with Digital Frequency Calibration and Improved HVM Screening

High-speed Low-power Clock Dividers for Phase-locked Loops (Tutorial)

专利

已授权专利（2000–2024）

US10,848,353 - Multi-Tap Decision Feedback Equalizer (DFE) Architecture with Split-Path Summer Circuits

US10,708,093 - Supply Voltage Adaptation Via Decision Feedback Equalizer

US10,523,411 - Programmable Clock Data Recovery (CDR) System Including Multiple Phase Error Control Paths

US10,181,969 - High Performance Receiver with Single Calibration

US10,128,855 - Apparatus and Method for Clock Synchronization for Inter-Die Synchronized Data Transfer

US10,075,308 - Supply Voltage Adaptation Via Decision Feedback Equalizer

US10,063,253 - Summer Circuit Including Linearized Load

US9,973,176 - Circuits for Digital and Analog Controlled Oscillators

US9,735,813 - Method and Apparatus for Signal Edge Boosting

US9,641,184 - Compensation for Digitally Controlled Oscillator Apparatus and Method

US9,531,393 - Phase Frequency Detector

US9,455,727 - Open-Loop Voltage Regulation and Drift Compensation for Digitally Controlled Oscillator (DCO)

US9,413,364 - Apparatus and Method for Clock Synchronization for Inter-Die Synchronized Data Transfer

US9,379,743 - Method and Apparatus for Signal Edge Boosting

US9,215,104 - Floating Taps for Decision Feedback Equalizer

US9,071,253 - Compensation for Digitally Controlled Oscillator App. and Method

US8,981,822 - High Speed Dual Modulus Divider

US8,957,705 - Phase Frequency Detector

US8,843,093 - Low Power Squelch Detector Circuit

US8,749,289 - Multi-Phase Clock Generation Apparatus and Method

US8,520,428 - Combined Data Level-Shifter and De-Skewer

US7,421,052 - Oscillator Frequency Selection

US7,366,427 - Line Driver with Variable Bandwidth Control

US6,954,110 - Replica Cell for Ring Oscillator

US6,870,432 - Unilateral Coupling for a Quadrature Voltage Controlled Oscillator

US6,853,254 - Anti-Deadlock Circuit and Method for Phase-Locked Loops

近期专利申请（2020–2024）

Differential Magnetic Core Inductors in Silicon Wafer or THV/TGV

18/919,584 - 3D Die to Die Interconnect Clock Scheme